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INTEGRATED CIRCUITS
SA1638 Low voltage IF I/Q transceiver
Product specification IC17 Data Handbook 1997 Sept 03
Philips Semiconductors
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
DESCRIPTION
The SA1638 is a combined Rx and Tx IF I/Q circuit. The receive path contains an IF amplifier, a pair of quadrature down-mixers, and a pair of baseband filters and amplifiers. A second pair of mixers in the transmit path transposes a quadrature baseband input up to the IF frequency. An external VCO signal is divided down internally and buffered to provide quadrature local oscillator signals for the mixers. A further divider chain, reference divider and phase detector are provided to avoid the need for an external IF synthesizer. Rx or Tx path or the entire circuit may be powered down by logic inputs. On-board voltage regulators are provided to allow direct connection to a battery supply.
* High performance on-board integrated receive filters with
bandwidth tunable between 50-850 kHz
* Switchable alternative bandwidth setting available to allow
channel bandwidth flexibility in operation
* Designed for a widely used I and Q baseband GSM interface * Control registers power up in a default state * Optional DC offset trim capability to <200mV * Only a standard reference input frequency required, choice of 13,
26, 39 or 52MHz
FEATURES
* Fully compatible with SA1620 GSM RF front-end (see Figure 9)
APPLICATIONS
* Direct supply: 3.3V to 7.5V * Two DC regulators giving 3.0V output * Low current consumption: 18mA for Rx or 22mA for Tx * Input/output IF frequency from 70-400 MHz * Internal IF PLL for synthesizing the local oscillator signal
PIN CONFIGURATION
* IF circuitry for GSM 900MHz hand-held units * IF circuitry for PCN (DCS1800) hand-held units * Quadrature up and down mixer stage
LQFP Package
GNDREG1 TxIFOUTX TxIFOUT RxIF INX VccTxRx PONPLL RxIF IN VccCP GND1 GND2 GND3
48 47 46 45 44 43 42 VREG1 VREGF2 VREG2 GNDREG2 PON VBATT AOUT BOUT DCRES RESD RESA RESB 1 2 3 4 5 6 7 8 9 10 11 12
41 40 39 38 37 36 35 34 33 32 31 VEECP IREF LO INX LO IN ADJ IN CLK IN CLK INX LOCK STROBE CLOCK DATA VEEDIG
48-pin LQFP
CP 30 29 28 27 26 25 VccDIG
13 14 15 16 17 18 19 20 21 22 23 24 QTx INX QTx IN QRxOUT IRxOUT QRxOUTX IRxOUTX PONRx ITx INX ITx IN VREF PDTx
SR00524
Figure 1. SA1638 Pin Configuration
ORDERING INFORMATION
DESCRIPTION 48-Pin Thin Quad Flat Pack (LQFP) TEMPERATURE RANGE -40 to +85C ORDER CODE SA1638BE DWG # SOT313-2
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853-1818 18351
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
BLOCK DIAGRAM
GNDREG1
GNDREG2
VREGF2
V BATT
VREG1
PONRx BIAS RX V REF PDTx BIAS TX ITx INX ITx IN V.REG.1 V.REG.2
TxIFOUT TxIFOUTX
VREG2
RESD
RESA
RESB
PON
QTx IN
VCCTxRx
QTx INX
GND3 IRxOUT GND1 RxIF IN IRxOUTX
RxIF INX GND2
IF AMP
QRxOUT QRxOUTX
LO IN LO INX
/2
DC BUFFERS ADJUST STATUS REGISTER
DCRES AOUT BOUT
ADJ IN
LOCK CP IREF PONPLL VCCCP VEECP
/N
DC REGISTER
CHARGE PUMP
PHASE DETECTOR
TEST REGISTER
/
13, 26 39, 52
SYNTH REGISTER
SERIAL INPUT
DIG
DIG
DATA
CLK INX
CLOCK
CLK IN
V CC
V EE
STROBE
SR00525
Figure 2. SA1638 Block Diagram
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VREG1 VREGF2 VREG2 GNDREG2 PON VBATT AOUT BOUT DCRES RESD RESA RESB PONRx VREF QRxOUT QRxOUTX IRxOUT IRxOUTX QTx IN QTx INX ITx IN ITx INX PDTx VCCDIG VEEDIG DATA CLOCK STROBE LOCK CLK INX CLK IN ADJ IN LO IN LO INX IREF VEECP CP VCCCP POnPLL GND3 TxIFOUTX TxIFOUT GND2 RxIF INX RxIF IN GND1 VCCTxRx GNDREG1 Output voltage of regulator 1 Feedback of regulator 2 Output voltage of regulator 2 Ground of regulator 2 Power-on input for voltage regulators 1 and 2 (active high) Input voltage for regulators 1 and 2 Programmable logic output (see Figure 9) Programmable logic output (see Figure 9) Reference current setting resistor for DC offset circuit Additional external current defining resistor for filters Principal external current defining resistor for filters Principal external current defining resistor for filters Power-on input for Rx (active high) Reference voltage Differential receive baseband output Differential receive baseband output Differential receive baseband output Differential receive baseband output Differential transmit baseband input Differential transmit baseband input Differential transmit baseband input Differential transmit baseband input Power-on for transmitter (active low) Digital circuit supply Digital ground Serial bus data input Serial bus clock input Serial bus strobe input Test control/synthesizer lock indicator Differential reference divider input Differential reference divider input Used for test only. Do not connect Differential LO input Differential LO input Reference current setting for charge pump Charge pump ground Charge pump output Charge pump circuit supply Power-on input for synthesizer circuits (active high) Ground (internal connection to GND1 and GND2) Differential transmit IFoutput (open collector) Differential transmit IFoutput (open collector) Ground (internal connection to GND1 and GND3) Differential receive IF input Differential receive IF input Ground (internal connection to GND2 and GND3) Transmit and receive circuits supply voltage (also feedback of Regulator 1) Ground of regulator 1 Description
NOTE: There are no ESD protection diodes at Pins 41 and 42. Thus, open collector outputs may have increased DC voltage or higher AC peak voltage.
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCCXXX VBATT VIN VG PD TJMAX PMAX TSTG Battery voltage Voltage applied to any other pin Any GND pin to any other GND pin Power dissipation, TA = 25C (still air) Maximum operating junction temperature Maximum power input/output Storage temperature range PARAMETER Supply voltages: VCCTxRx, VCCDIG, VCCCP RATING -0.3 to +6.0 -0.3 to +8.0 -0.3 to (VCCXXX+0.3) 0 300 150 +20 -65 to +150 UNITS V V V V mW C dBm C
NOTE: 1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, JA. 48-pin LQFP: JA = 67C/W.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCCXXX VCCCP VBATT TA Charge pump supply voltage Battery voltage Operating ambient temperature range PARAMETER Supply voltages: VCCTxRx, VCCDIG RATING 2.7 to 5.5 2.9 to 5.5 3.3 to 7.5 -40 to +85 UNITS V V V C
Voltage Regulators
TA = 25C, PON = 3V, PONRX = 0V, PDTX = 3V, PONPLL = 0V, VBATT = 3.3V, IOUT1 = IOUT2 = 15mA, VREG1 connected to VCCTxRx, VREG2 connected to VREGF2; VCCDIG = VCCCP = 3V; unless otherwise stated. SYMBOL VREG1, VREG2 VBATT IOUT1, IOUT2 IBATT IBATT PD CREG12 CREG22 LINEREG LOADREG BW FPON Maximum output current for each regulator1 Supply current for both regulators Power-down supply current VREG1 cap load VREG2 cap load Line regulation Load regulation Bandwidth Feedthrough attenuation from PON to each regulator Feedthrough attenuation from VBATT to each regulator Turn ON time f 100kHz f = 10MHz f = 100MHz f = 400MHz DC, VBATT = 3.3V to 7.5V ILOAD = 15mA to 30mA ILOAD = 0mA PON = 0V, ILOAD = 0mA 0.1 0.1 -0.4 -5 100 -40 -61 -32 -37 -48 10 -0.2 -0.37 0.001 -0.17 0.2 0.03 4.3 7.7 5 9 5.7 10.3 PARAMETER Nominal VOUT TEST CONDITIONS LIMITS Min 2.85 3.3 -3 2.93 Typ 3.00 +3 3.07 Max 3.15 7.5 30 7 15 1000 500 0.4 5 UNITS V V mA mA A F F % % kHz dB
FREG tON
dB s
NOTES: 1. At Tj 150C a thermal switch reduces the output current to avoid damage. 2. Recommended load capacitors: In every case CREG1 = CREG2 = 100nF to ground with series resistance 0.1. Additional capacitor optional 1000F with series resistance 5. The low series resistance is very important to ensure regulator stability. 3. Standard deviations are based on the characterization results of 90 ICs.
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
DC ELECTRICAL CHARACTERISTICS
VCCTxRx=VCCDIG=VCCCP=PONRx=PONPLL= +3V; VEEDIG = VEECP=GND1=GND2=GND3=PDTx = 0V; TA = 25C, unless otherwise stated. SYMBOL PARAMETER Supply current Rx and IF synthesizer active ICC Tx and IF synthesizer active Power-down mode VREF IVREF IOUT Reference voltage VREF ISINK ISOURCE At pins TxIFOUT and TxIFOUTX 1.5 1.86
PONRx = PONPLL = PDTx = Hi PONRx = PDTx = Low; PONPLL = Hi PONRx = PONPLL = Low; PDTx = Hi
TEST CONDITIONS
LIMITS MIN -3 14.4 17.4 TYP 16 19.5 0.068 1.39 1.57 5 5 2.0 2.14 2.7 1.75 +3 17.6 21.6 MAX 20 24
UNITS
mA
Generated internally
V A mA
DC output current
Digital inputs (PON) VIH VIL VIH VIL VIH VIL VOH VOL High level input voltage range Low level input voltage range High level input voltage range Low level input voltage range High level input voltage range Low level input voltage range Output voltage HIGH Output voltage LOW IO = -2mA IO = 2mA 2.0 0 2.0 0
2.0
VBATT 0.8 VCCTxRx 0.8 VCCDig
0.8
V V V V V V V
Digital inputs (PDTx, PONRx, PONPLL, PON)
Digital inputs (Clock, Data, Strobe) 0
VCCDIG-0.4
Digital outputs (LOCK, AOUT, BOUT) 0.4 V
AC ELECTRICAL CHARACTERISTICS
VCCTxRx=VCCDIG=VCCCP=PONRx=PONPLL= +3V; VEEDIG = VEECP=GND1=GND2=GND3=PDTx = 0V; LOIN = 100mVPEAK, 800MHz; CLKIN = 100mVPEAK, 52MHz; serial registers programmed with default values; TA = 25C unless otherwise stated. Test Circuit Figure 8. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN -3 0.82 1 TYP 0.94 1.5 0.75 -61 -57 -53 -40 +3 1.06 2 MAX UNITS
IF Transmit Modulator BW VCOM VIN Input modulation bandwidth Common mode range for baseband inputs Peak input signal amplitude Third harmonic distortion1 200 source impedance DC at pins ITxIN, ITxINx, QTxIN, QTxINx Centered on VCOM | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20kHz Between pins: ITxIn and ITxInX or QTxIn and QTxInX At ITxIn, ITxInX, QTxIn, QTxInX | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20k | ITxIn | = | ITxInX | = | QTxIn | = | QTxInX | = 0.75VPEAK; fin = 20k 112 10 VCCTxRx-0.3 0.6 0.73 0.82 0.91 1.08 MHz V V dB
RINTx CINTx
Input resistance Input capacitance Output saturation limit
k pF V mA
IOUT
RMS output current
SLO
LO suppression1
+30
+43
dB
SSB
Sideband suppression1
+35
+50
dB
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN -3 -130 -133 TYP -129 -131 5 5 5 || 0.6 1 VREF 70 6.5 30 8.9 38.1 83 10.7 45 70 >80 >80 51 7.0 -0.26 0.0 -25 10 (700) 2.0 -59 -54 -55.3 -49.3 -53 -47 -47 -47 2 2 -50.7 -44.8 -47 -40 12.5 51.9 90 +3 -128 -129 MAX UNITS
IF Transmit Modulator (continued) Noise density at 600kHz Noise density at 10MHz tON tOFF RInRx ROutRx f3dB Turn ON time Turn OFF time Differential input impedance Output impedance Output common mode voltage Low pass filter -3dB bandwidth Low pass filter attenuation: 200kHz 400kHz 600kHz 6.5MHz 13.0MHz VG NF Voltage gain Noise figure8 Channel matching: Gain Phase Output DC offset2 IOUT VOUT Output drive current at each pin Minimum differential output swing Input 1dB compression point: In band 200kHz 400kHz 600kHz Turn ON time3 Turn OFF time Differential output PD into GSM baseband relative to 1200 source EMF 1200 source and external matching resistor and inductor fIN = 400.005MHz Differential, DCRES=562k Source (Sink) -1.5 -60 |ITxIn| = |ITxInX| = |QTxIn| = |QTxInX| = 0.75VPEAK PdTx = LO, transmit signal to 90% PdTx = HI, transmit signal to 10% fIN = 400MHz dBc/Hz s s k || pF k V kHz
IF Receiver (R = 36k between pins RESA and RESB)
dB
43
49.4 5.7
52.7 8.3
58
dB dB
1.5 60
dB degrees mV A V
P-1dB
1200 source EMF
dBV
tON tOFF
POnRx = HI, to baseband signal out POnRx = LO, to no baseband signal out
s s
IF Synthesizer fLO ZLOIN VLOIN Local oscillator input frequency range9 Differential input impedance LO peak input voltage range Programmable divider: Division range Step size fCLKIN ZCLKIN VCLKIN IREF Reference clock input frequency Differential input impedance CLKIN peak input voltage range Charge pump input reference current Charge pump output current: c0...c2 = 000 c0...c2 = 111 Step size IREF =31.2A, VCP = VCCCP/2 0.425 0.85 0.045 0.487 0.979 0.062 VCLKIN = 100mVPEAK Between pins ClkIn and ClkInX Single-ended, referred to 50 50 31.2 0.5 1.0 0.071 0.513 1.021 0.08 0.575 1.15 0.105 10 || 1.0 400 Between pins LOIN and LOINX, fIN = 800MHz Single-ended Referred to 50 50 64 1 52 MHz k || pF mV A 140 276 || 0.6 100 511 800 MHz || pF mV
| ICP |
mA
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN -3 TYP +3 MAX UNITS
IF Synthesizer (cont.) DI CP I CP ICP_M |ICP_L| tON tOFF Relative output current variation4 Output current matching5 Output leakage current Turn ON time Turn OFF time6 IREF =31.2A IREF =31.2A, VCP = VCCCP/2 VCP = 0.3V to VCCCP-0.3V POnPLL = HI, to full charge pump current POnPLL = LO, to ICCCP, ICCDIG <5% of operational supply current -0.02 0.1 15 15 0.22 0.1 1.3 2.5 10 12 15 % % nA s s
Serial Interface7 fCLOCK tSU tH tW Clock frequency Set-up time: DATA to CLOCK, CLOCK to STROBE Hold time: CLOCK to DATA Pulse width: CLOCK Pulse width: STROBE 30 30 30 30 10 MHz ns ns ns
NOTES: 1. Parameter measured relative to modulation sideband amplitude. 2. After programming the DC offset register for minimum offset. DCRES = 562k. 3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for GSM-mode = 8s with filter bandwidth setting resistor = 36k). DI OUT (I * I 1) 4. The relative output current variation is defined thus: +2@ 2 ; with V1 = 0.3V, V2 = VCCCP - 0.3V (see Figure 3). |(I 2 ) I 1)| I OUT 5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on. 6. As soon as PONPLL is set to LO, the phase detector is reset and no charge pumps pulses are generated. 7. Guaranteed by design. 8. NF = 20 log E no 4kTR * VG where, Eno is the output noise voltage measured in a 1Hz bandwidth, R = 1200, VG = gain in dB.
9. Minimium frequency is guaranteed by design.
CURRENT I2 I1
VOLTAGE V1 V2
address bits and 1 subaddress bit. Figure 2 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the value of the subaddress bit the data is latched into different working registers. Table 3 shows the contents of each word.
Default States
Upon power up (VCCDIG is applied) a reset signal is generated, which sets all registers to a default state. The logic level at the STROBE pin should be low during power up to guarantee a proper reset. These default states are shown in Table 3.
SR00526
I2 I1
Reference Divider
The reference divider can be programmed to four different division ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide by 13.
Figure 3. Relative Output Current Variation
FUNCTIONAL DESCRIPTION Serial Programming Input
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program the counter ratios, charge pump current, status- and DC-offset register, mode select and test register. The programming data is structured into two 21-bit words; each word includes 4 chip
Main Divider
The external VCO signal, applied to the LOIN and LOINX inputs, is divided by two and then fed to the main divider (:N). The main divider is a programmable 9 bit divider, the minimum division ratio is
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
divide by 64. The division ratio is binary coded and set in the registers n0 to n8. The default setting is a divide by 400. At the completion of a main divider cycle, a main divider output is generated which will drive the phase detector.
Status Register
The s0 and s1 status bits determine the values of the logic output pins AOUT and BOUT. These outputs can be connected to the AGC control inputs A and B of the SA1620. (See Figure 9)
Phase Detector
The phase detector is a D-type flip-flop phase and frequency detector shown in Figure 5. The flip-flops are set by the negative edges of the output signals of the dividers. The rising edge of the signal L will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump acts to increase the VCO frequency; a sink current acts to decrease the VCO frequency.
DC Offset Register
Registers i0 to i3 and q0 to q3 control a correction to the output DC offset of the I and Q channels of the receiver. The polarity of the DC offset correction in the I and Q channels are determined by i0 and q0, respectively. The other bits set the magnitude of the offset correction. The step size of the two offset correction DACs is fixed by an external resistor between the DCRES pin and ground. A value of 120k will give a step size of 200mV.
Mode Select Register
t0: switches the RX IF gain. t0 = 0 no attenuation t0 = 1 10dB attenuation
Current Setting
The charge pump current is defined by the current set between the pin IREF and VEECP. The current value to be set there is 31.2A. This current can be set by an external resistor to be connected between the pin IREF and VEECP. The typical value REXT (current setting resistor) can be calculated with the formula R EXT + V CCCP * 1.4V 31.2mA
The attenuation switch is included between the IF amplifier and the I and Q mixers, thereby influencing the noise figure negligibly. The purpose of this switch is to provide another AGC step which does not influence the receiver noise figure. Please note that this gain change will influence the DC offset of the I and Q mixers. t1 = 0 test mode only, always to be set to 0. t2, t3 sets the mode of the level locked loop (LLL) The LLL is a circuit which processes the LO input signal in order to provide an LO signal with a perfect 50% duty cycle, which determines the precision of the 90 shift of the I and Q mixing signals generated by the /2 divider. For an external tuning of the 90 phase shift of the I and Q mixing signals, a trimming resistor may be connected (but is not required) between the ADJIN pin and ground, and the LLL has to be put in one of the following modes:
The current can be set to zero by connecting the pin IREF to VCCCP.
Charge Pumps
The charge pumps at pin CP are driven by the phase dectector and the current value is determined by the binary value of the charge pumps register CN = c2, c1, c0, default 1mA. The active charge pump current is typically: |I CP| + (c0 ) 2c1 ) 4c2) @ 71mA ) 500mA
Table 2.
t2 0 0 1 1 t4 t3 0 1 0 1
Mode Select Register
LLL Status LLL on (no external tune, monitor performance, default) LLL on (with medium external tune) LLL off (tune externally) LLL on (with fine external tune)
Lock Detect
The output LOCK is H when the phase detector indicates a lock condition. This condition is defined as a phase difference of less than 1 cycle on the reference input CLKIN, CLKINX.
Test Modes (Synthesizer, Transmit Mixer)
The LOCK output is selectable as a test output. Bits x0, x1 control the selection, the default setting is normal lock output as described in the Lock detect section. The selection of a Bit x0, x1 combination has a twofold effect: First it routes a divider output signal to the LOCK pin, second it disables mixer stages in the transmit path. Setting x0,1 = 11 disables both transmit path mixers. This mode can be used to prevent the transmitter from producing an IF output signal even if the transmit part is powered on (PDTx = 0V). This can be used to simplify the control timing while commanding the transmit and receive simultaneously without the transmit part causing interference.
t5
selects the bandwidth of the RC low pass filters at the I, Q Rx mixer outputs t4 = 0 cutt-off frequency (-3dB) 110kHz t4 = 1 cutt-off frequency (-3dB) 792kHz selects the bandwidth of the integrated 5th-order gyrator filters. The filters are tuneable over a range of 50kHz to 1MHz with external resistors. The -3dB bandwidth is inversely proportional to the value of the external resistor. t5, two external resistor values are selectable. t5 = 0 the resistance between the pins RESA and RESB determines the cutoff frequency. For GSM a nominal bandwidth of 80kHz is chosen when the external resistor is 36k. t5 = 1 a second resistor between the pins RESB and RESD is connected in parallel to the first external resistor, thus increasing the filter bandwidth. The relative amplification is decreased in this mode.
With
Table 1.
x0 0 1 0 1 x1 0 0 1 1
Test Modes
Synthesizer Signal y g at LOCK Pin normal lock detect CLKIN divided by reference divider ratio LOIN / 2 * (main divider ratio) main divider output, that goes to the phase detector Transmit Mixer Q-mixer on off on off I-mixer on on off off
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
The overall filter response in the receive section is the sum of the filter responses of the passive RC low-pass filter and the active gyrator filter.
PONRx = H powers up the receiver part. PDTx = L powers up the transmitter part. PONPLL = H powers up the synthesizer part. As it also powers up the first divide by 2 stage for generating the 0/90 degree phase shifted signals for the transmit and receive mixers, it also has to be set H if either the transmit part or the receive part is used. PONPLL = L powers down the dividers, resets the phase detector and disconnects the current setting pin IREF. In PONPLL = L mode, the values in the serial input registers are still kept and the part still can be reprogrammed as long as VCCDIG is present.
Power Down Modes
There are 4 power-on pins in the SA1638: PON, PONRx, PDTx, PONPLL. PON = H powers up both voltage regulators VREG1 and VREG2. PON should be set to L, if these internal voltage regulators are not to be used.
Table 3. Definition of SA1638 Serial Registers
First data word: (shown with default values) Address SA1638
MSB
Sub Adr
N-Divider
Ref / Reg
Charge-Pump
Reg Test
LSB
a0 1
a1 1
a2 1
a3 0
sa 0
n0 1
n1 1
n2 0
n3 0
n4 1
n5 0
n6 0
n7 0
n8 0
r0 0
r1 0
c0 1
c1 1
c2 1
x0 0
x1 0
Address: Sub:Address: N-Divider: Reference Divider Register: Charge-Pump Register: Test Register:
4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 0 for first data word 9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400 2 bits, r0...r1, 00 = /13, 01 = /26, 10 = /39, 11 = /52. Default: 00 3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 = maximum current, default maximum charge pump current 2 bits, x0...x1, default 00, see Functional Description
Second data word: (shown with default values) Address SA1638
MSB
Sub Adr
Status Reg
DC Offset Register Q-Channel I-Channel Mode Select Register
LSB
a0 1
a1 1
a2 1
a3 0
sa 1
s0 1
s1 1
q0 0
q1 0
q2 0
q3 0
i0 0
i1 0
i2 0
i3 0
t0 0
t1 0
t2 0
t3 0
t4 0
t5 0
Address: Sub:Address: Status Register: DC Offset Register:
4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 1 for second data word 2 bits, s0 sets pin AOUT; s1 sets pin BOUT, see Functional Description 4 bits per channel, i0...i3 and q0...q3, no correction as default i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage il...i3 and q1...q3, 000 no correction to 111 max. correction enabled 6 bits, t0...t5, 000000 = normal GSM-Operation as default, see Functional Description
Mode Select Register:
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
LSB DATA X1 or t5 X0 or t4 tH tSU 50% CLOCK FIRST CLOCK a1
MSB a0
tSU
LAST CLOCK
FIRST CLOCK
tSU
STROBE CLOCK ENABLED SHIFT IN DATA tW 50% CLOCK DISABLED STORE DATA
CLOCK STROBE
SR00527
Figure 4. Serial Input Timing Sequence
L "1" CLKIN REFERENCE DIVIDER R R P P-TYPE CHARGE PUMP D C Q VCCCP
"1" LOIN
D C
R
CP
/2
MAIN DIVIDER
X Q N N-TYPE CHARGE PUMP
VSS
CLKIN
L
R
X
P
N
ICP
SR00528
Figure 5. Phase Detector Structure with Timing
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Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN FUNCTIONS
PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT
5
PIN PIN DC V No. MNEMONIC
EQUIVALENT CIRCUIT
47
VCCTxRx
3.0
BG 1.2 -- +
2.5
6
10
RESD
0.05
10
1 35k
t5
48
GNDREG1
0.0
25k
47
11
48
RESA
0.00
11 40 43 46
1 2 3 4
VREG1 VREGF2 VREG2 GNDREG2 PON VBATT
3.0 3.0
BG 2.5
40
43
46 5
6
3.0 0.0
1.2 -- + 3 35k 2
12
RESB
0.05
5 6
3.3 3.3
25k 4 12 40 43 46
7
13
PONRx
3.0
13
7
AOUT
3.0
14
8
VREF
1.5
14
8
BOUT
3.0
15
QRXOUT QRXOUTX
1.5
9
16
1.5
15, 17 16, 18
9
DCRES
1.6
17
IRXOUT
1.5
18
IRXOUTX
1.5
SR00529
Figure 6. Pin Functions 1997 Sept 03 12
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN FUNCTIONS (continued)
PIN PIN DC V No. MNEMONIC 19 20 21 22 QTXIN QTXINX ITXIN ITXINX 1.5 1.5 1.5 1.5 36 VEECP 0.0
19, 20, 21, 22
EQUIVALENT CIRCUIT
PIN PIN DC V No. MNEMONIC
EQUIVALENT CIRCUIT
35
IREF
1.6
35
23
PdTx
0.0
23
37
CP
37
24 25 26 27
VCCDIG VEEDIG DATA CLOCK
3.0 3.0
38
VCCCP
3.0
39
PONPLL
3.0
39
26, 27, 28
40 28 STROBE 41 29 LOCK
29
GND3
0.0
OPEN COLLECTOR 41 42
TXIFOUTX
42 30 CLKIN 2.0
30 31
TXIFOUTX
43
GND2
0.0
31
CLKINX
2.0 44 RxIFINX 1.5
44 45
32
ADJIN
2.0
32
45
RxIFIN
1.5 VREF
46 33 LOIN 2.0 47
33 34
GND1
0.0
VCCTxRx
3.0
34
LOINX
2.0
48
GNDREG1
0.0
SR00530
Figure 7. Pin Functions (cont.) 1997 Sept 03 13
OPEN COLLECTOR
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
Overview of Dual GSM/PCN Architecture
The SA1620 RF front-end and SA1638 IF transceivers form a dual conversion architecture which uses a common IF and standard I/Q baseband interface for both transmit and receive paths. The time division multiplex nature of the GSM system permits integration of the transmit and receive functions together on the one RF and one IF chips. This simplifies the distribution of local oscillator signals, maximizes circuitry commonality, and reduces power consumption. The SA1620 and SA1638 allow considerable flexibility to optimize the transceiver design for particular price/size/performance requirements, through choice of appropriate RF and IF filters. The IF may be chosen freely in the range 70-400 MHz. The same IF can be used in the transmit and receive directions. Alternately, different IFs can be used if the SA1638 synthesizer frequency is switched between transmit and receive timeslots. The comparison frequency of the SA1638 PLL is high in order to provide fast switching time. With suitable choice of the IF, an identical SA1638 IF receiver design can be used for both 900MHz GSM and 1800MHz PCN (DCS1800) equipment.
output power can be reduced to an appropriate level by choice of an external resistor.
* DC offsets generated in the receive channel are independent of
the LNA AGC setting, and correctable by software to prevent erosion of signal handling dynamic range by DC offsets.
* Minimal high-quality filter requirements.
As a result of the integration in the SA1638 of high quality channel selectivity filters, only sufficient filtering is needed in the receive path to provide blocking protection for the second mixers. This reduces receiver cost and size. to be relaxed. For example, at a 400MHz IF, the natural gain roll-off in the SA1620 LNAs and mixer suppresses the image signal in the 1800MHz band by typically 28dB below the desired 900MHz band signal.
* Operation at a high IF allows RF image reject filter requirements
DC Offset Correction
DC offset correction is provided by two DACs each feeding into one of the two Rx channels. The step size of both DACs is set by the value of the external resistor between DCRES and ground. Thus any original offset less than 1.5V magnitude in either channel can be reduced to the specified level by selecting the appropriate DAC setting via the serial interface.
General Benefits/Advantages
* 2.7V operation.
Compatible with 3V digital technology and portable applications. (Higher voltage operation also possible, if desired.) The availability of two LNAs in the SA1620 allows flexibility in receiver dynamic design for portable and mobile GSM spec. applications with appropriate filters. If for a particular application a GaAs or discrete front-end is desired, one of the LNAs can be left unpowered. Placing the AGC gain switches at the front results in some attenuation most of the time, further increasing typical dynamic performance beyond that specified by GSM. This is sufficient to drive a filter and power amplifier input, without a driver amplifier. To avoid unnecessary current consumption, the
Integrated Receive Filters
The low-pass characteristics of the Rx channel are determined by two low-pass responses. The first of these is a passive filter at the output of the quadrature mixers and the second is the low-pass filters which follow the post-mixer amplifiers. These specifications refer only to the response of the default state, but this may be switched by the control register to an alternative setting with a nominal 3dB point of 792kHz. The corner frequency of the low pass filters can be adjusted over a wide range by varying the value of the external resistor between RESA and RESB. The range of feasible corner frequencies extends at least between 50kHz and 500kHz.
* Excellent dynamic range.
* High power transmit output driver, delivering +7.5dBm output.
1997 Sept 03
14
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
1 100nF 2 0-30mA 3 100nF 4 0-30mA PON 1nF VBATT 100nF AOUT 7 6 5
VREG1
GNDREG1
48
VREGF2
VCCTxRx
47
3V
VREG2
GND1
46 1.8pF RxIN TC4-14 2.5k
GNDREG2
RxIFIN
45 33nH 1800 1.8pF 2:1 51.4
PON
RxIFINX
44
51.4
VBATT
GND2
43 TxOUT TC4-14 17.4 42 294 294
AOUT
TxIFOUT
BOUT
8
BOUT
TxIFOUTX
41 2:1
9 112k 1M 22k 11 56k 12
DCRES
GND3
40
1nF
2-3V
10
RESD
39 PONPLL 1nF 100nF 38 VCCP 37 10nF
PONPLL
RESA
VCCP
RESB
CP
VCP
PONRx
13 PONRx VEECP
36 VCO 800MHz 10nF 4740 17.4 294 4.7nF 470pF LOIN
VREF
14
VREF
IREF
35
15
QRxOUT
LOINX
34
10k
16
QRxOUTX
LOIN
33
10nF
294
Rx OUT
+ 10k - 10k
17
IRxOUT
32 ADJIN 31 10nF 1nF 17.4 49.9 294 294 10nF
ADJIN CLKIN
18
IRxOUTX
CLKIN
19 10k I/Q 2.7pF GEN 21 DC - 1MHz 22 20
QTxIN
CLKINX
30
QTxINX
LOCK
29
LOCK
ITxIN
STROBE
28 10pF
STROBE
ITxINX
CLOCK
27 10pF
CLOCK
3-WIRE SERIAL
PD Tx 1nF VCC DIG 1nF 10nF
23
PDTx
DATA
26 10pF
DATA
BUS
24
VCC DIG
VEE DIG
25
SR00531
Figure 8. SA1638 Test Circuit
1997 Sept 03
15
1997 Sept 03
INTERFACE TO MICROCONTROLLER
Philips Semiconductors
PCA5075 SERIAL POWER AMP INPUT CONTROLLER
SA1620 SA1638
400MHz SSB MIXER LINEAR IF LEVEL CONTROL
I I Q
PA
BUFFER POWER SUPPLY Tx/Rx 400MHz
LO1 (1290-1360MHz)
Q I I VAR LPF Q Q
Low voltage IF I/Q transceiver
Tx: 935-960MHz ATTENUATION CONTROL LOGIC SAW LO2 800MHz
A
B
Rx: 890-915MHz
/ /
Figure 9. SA1620 / SA1638 System Block Diagram
PD PD LNA2 FREQUENCY SYNTHESIZER (SA8025, UMA1019) LNA1
16
/
CLKIN 13MHz AOUT BOUT (to SA1620 ATTENUATION CONTROL LOGIC INPUTS)
INTERFACE TO MICROCONTROLLER
SR00532
Product specification
SA1638
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS
Regulator Dropout Voltage vs. Temperature and VBATT
5 7.5V 4.5 4 VOLTAGE (V) CURRENT (mA) 3.5 3 2.5 2 1.5 1 0.5 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 3.3V 5.5V ILOAD=30mA
7
Regulator Supply Current vs. Temperature and VBATT
6.5 6 5.5 5 4.5 4 3.5 3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) 3.3V 5.5V 7.5V No Load
Regulator Powerdown Supply Current vs. Temperature and VBATT
40 35 30 0.4 25 5.5V 20 15 3.3V 10 5 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 REGULATION (%) CURRENT ( A) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 3.3V 7.5V 5.5V 7.5V 0.6 1 0.8
Regulator Load Regulation vs. Temperature and VBATT
ILoad = 15mA to 30mA
-50 -40 -30 -20 -10
0 10 20 30 Temperature (C)
40
50
60
70
80
90
Regulator Line Regulation vs. Temperature and VBATT
0.4 0.3 ILOAD =15mA REGULATION (%) 0.2 0.1 0 3.3V -0.1 -0.2 2.9 -0.3 -0.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) 2.85 5.5V VOLTAGE (V) 7.5V 3.15 3.3V 3.1 3.05 3 2.95 5.5V 7.5V
Regulator Output Voltage vs. Temperature and VBATT
ILOAD =15ma
-50 -40 -30 -20 -10
0 10 20 30 Temperature (C)
40
50
60
70
80
90
Figure 10. Typical Performance Characteristics
1997 Sept 03
17
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Output Second Harmonic Distortion Transmitter Input Modulation Bandwidth vs. Temperature and VCCTxRx
1100.0 FREQUENCY (kHz) 1050.0 1000.0 950.0 900.0 850.0 2.7V 5.5V 4.0V 3.0V -30 -10 10 30 Temperature (C) 50 70 90 ITXIN=ITXINX=QTXIN=QTXINX=1.5Vpp SECOND HARMONIC LEVEL (dBc) -55 Tx In = 1.5VP-P -50
4V -60 3V 5.5V 2.7V
800.0 -50
-65
Transmitter Output Third Harmonic vs. Temperature and VCCTxRx
-50 TXIN=1.5VP-P -55 2.7V 3V 4V -60 5.5V
-70 -50 0 Temperature (C) 50 100
DISTORTION LEVEL (dBc)
Transmitter Output Fourth Harmonic Distortion
-60
-65 Tx In = 1.5VP-P FOURTH HARMONIC LEVEL (dBc) -65 2.7V 4V -70 3V 5.5V -70 -50
-30
-10
10 30 Temperature (C)
50
70
90
Transmitter Output Fifth Harmonic Distortion
-60
-75
Tx In = 1.5VP-P FIFTH HARMONIC LEVEL (dBc) -65 3V 4V -80 -50 5.5V -70 0 Temperature (C) 50 100
-75
-80 -50 0 Temperature (C) 50 100
Figure 11. Typical Performance Characteristics (continued)
1997 Sept 03
18
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Output Saturation vs. Temperature and VccTxRx
5th HARMONIC DISTORTION LEVEL (dBc) -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) 2.7V 3.0V 4.0V 5.5V TXIFOUT=TXIFOUTX=VccTxRx-0.3V RMS CURRENT (mA) 1.1 1.05 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) 5.5V 4.0V 3.0V 2.7V IF=400MHz
Transmitter RMS Output Current vs. Temperature and VCCTxRx
Transmitter DC Output Current vs. Temperature and VCCTxRx
2.5 2.4 SUPPRESSION (dBc) 2.3 CURRENT (mA) 2.2 2.1 2 1.9 1.8 1.7 1.6 1.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) -48.0 -50.0 5.5V 4.0V 3.0V 2.7V -36.0 -38.0 -40.0 -42.0 -44.0 -46.0
Transmitter LO Suppression vs. Temperature and VccTxRx
5.5V 4.0V 3.0V 2.7V
-50 -40 -30 -20 -10
0 10 20 30 Temperature (C)
40
50
60
70
80
90
Transmitter Side Band Suppresion vs. VCCTxRx and Temperature
-35 -40 SUPPRESSION (dBc) 5.5V -45 4.0V 3.0V -50 2.7V -55 -60 -65 -70 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 OUTPUT NOISE (dBc/Hz)
Transmit Noise Floor vs Temperature and Supply Voltage
-126 Baseband Input = 1.5VP-P differential, 30kHz -127 -128 -129 -130 -131 -132 -133 -134 -135 -136 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 5.5V 4V 3V 2.7V 5.5V 4V 3V 2.7V 10MHz from Carrier 600kHz from Carrier
Figure 12. Typical Performance Characteristics (continued)
1997 Sept 03
19
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Input Common Mode Range Vs. Supply Voltage
0
Receiver 3dB Bandwidth vs. Temperature and VCCTxRx
100.0
90.0 -20 5th HARMONIC dBc T = +25C FREQUENCY (kHz) 80.0 2.7V 3.0V 4.0V 70.0 5.5V
2.7V -40
3.0V
4.0V
5.5V
60.0
-60 50.0
-80 0 1 2 3 4 5 6 COMMON MODE VOLTAGE
40.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C)
Receiver NF vs Temperature and Supply Voltage Receiver Gain vs. Temperature and VCCTxRx
60.0 58.0 56.0 GAIN (dB) 54.0 52.0 50.0 48.0 46.0 44.0 42.0 40.0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 4 2 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 5.5V 4.0V 3.0V 2.7V NF (dB) IF=400.005MHz, LO=400MHz 14 12 Relative to 1200 source resistance 16
2.7V
10 8 6 3V 5.5V 4V
Receiver Gain match vs VCCTxRx and Temperature
1 0.8 0.6 0.4 MATCH (dB) ERROR (o) 0.2 0 -0.2 -0.4 2.7V -0.6 -0.8 -1 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 3.0V 4.0V 5.5V 5 4 3 2 1 0 -1 -2 -3 -4 -5 5.5V
Receiver Channel Matching Phase Error vs. Temperature and VCCTxRx
2.7V 3.0V 4.0V
-50 -40 -30 -20 -10
0 10 20 30 Temperature (C)
40
50
60
70
80
90
Figure 13. Typical Performance Characteristics (continued)
1997 Sept 03
20
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Receiver Corrected Output Offset Voltage vs. Temperature and VCCTxRx
200 150 100 OFFSET (mV) LEVEL (dBm) 50 0 -50 -100 -150 -200 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 -57.0 -59.0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 5.5V 4.0V 2.7V 3.0V -51.0 5.5V -53.0 -55.0 3.0V 4.0V 2.7V DCRes Resistor=100k -49.0 -47.0
Receiver In-band 1dB Compression Point vs. Temperature and VCCTxRx
SA1638 Receiver QRXOUT Voltage
1.8 5.5V 1.8
Reference Voltage
5.5V 1.75
1.7 PIN 15 DC VOLTAGE (V) 1.7 4V 1.6 VREF (V) 1.65 4V 1.6 1.55 1.5 2.7V 2.7V 1.5 3V
3V
1.4 -50 0 50 TEMPERATURE (C) 100
1.45 -50 0 50 TEMPERATURE (C) 100
Receiver IP2 vs Temperature and Supply Voltage
1100 5.00 4.00 3.00 2.00 IP2 (dBm) 1.00 0 -1.00 -2.00 -3.00 -4.00 -5.00 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 900 -50 5.5V 4V 3V FREQUENCY (MHz) 1050
LOIN Maximum Frequency Div800
VLOIN = 100mVPEAK
3V
1000
2.7V
4V
2.7V
950 5.5V
0 50 TEMPERATURE (C)
100
Figure 14. Typical Performance Characteristics (continued)
1997 Sept 03
21
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
CLKIN Maximum Frequency Div52
250 2.7V 3V 225 4V CURRENT ( A) 200 -505 4V -510 -495 2.7V -500 3V
N Charge Pump Output Current 000
FREQUENCY (MHz)
-515 5.5V
175 5.5V 150 -50
VCLKIN = 100mVPEAK
-520
0 50 TEMPERATURE (C)
100
-525 -50 0 50 TEMPERATURE (C) 100
P Charge Pump Output Current 111
-1000 2.7V -1010 1 CURRENT ( A) -1020 3V VARIATION (%) 0.75 1.25
N Charge Pump Relative Output Variation
5.5V
4V -1030
0.5 4V 0.25 2.7V 3V
-1040 5.5V -1050
-1060 -50 0 50 TEMPERATURE (C) 100
0 -50 0 50 TEMPERATURE (C) 100
Charge Pump Match Current 111
-20 2.7V 0.25
Charge Pump Output Leakage Current
2.7V -30 CURRENT ( A) 3V CURRENT (nA) 0 3V 4V -0.25 5.5V
4V -40
-50 5.5V
-0.5
-60 -50 0 50 TEMPERATURE (C) 100
-0.75 -50 0 50 TEMPERATURE (C) 100
Figure 15. Typical Performance Characteristics (continued)
1997 Sept 03
22
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Supply Current vs. Temperature and VCCTxRx
26 24 22 CURRENT (mA) 5.5V 4.0V 3.0V 2.7V CURRENT (mA) 20 18 16 14 12 10 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 20 19 18 17 16 15 14 13 12 11 10 2.7V 5.5V 4.0V 3.0V
Receiver Supply Current vs. Temperature and VCCTxRx
-50 -40 -30 -20 -10
0 10 20 30 Temperature (C)
40
50
60
70
80
90
Power Down Supply Current vs. Temperature and VCCTxRx
160 140 CURRENT ( A) 120 VOLTAGE (mV) 100 80 3.0V 60 2.7V 40 20 0 -50 -40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90 245 5.5V 4.0V 3.0V 2.7V -30 260 255 250 4.0V 5.5V 270
Receiver Uncorrected Output Offset Voltage vs Temperature and VCCTxRx
DCRES = 100k 265
240 -50
-10
10 30 TEMPERATURE (C)
50
70
90
Receiver Output Offset Control Step Size vs Temperature and VCCTxRx
330 320 VOLTAGE (mV) 310 300 290 280 -50 5.5V 4.0V 3.0V 2.7V DCRES = 100k VOLTAGE (mV) 37 36 35 34 33 32 -50 5.5V 4.0V 3.0V 2.7V
Receiver Output Offset Control Step Size vs Temperature and VCCTxRx
DCRES = 1M
-30
-10
10 30 TEMPERATURE (C)
50
70
90
-30
-10
10 30 TEMPERATURE (C)
50
70
90
Figure 16. Typical Performance Characteristics (continued)
1997 Sept 03
23
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
1997 Sept 03
24
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
NOTES
1997 Sept 03
25
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 08-98 Document order number: 9397 750 06847
Philips Semiconductors
1997 Sept 03 26

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